1. Technical Field
The present invention relates to a computer system in which a plurality of units of execution can be run on each processor core. More specifically, the present invention relates to a calculation method and apparatus for evaluating response time of a computer system in which a plurality of units of execution can be run on each processor core.
2. Background Art
Many high-performance processors have the function of processing a plurality of hardware threads in parallel on each processor core using a simultaneous multi-threading (SMT) technique. The SMT function can increase the peak throughput of servers by increasing the hardware resource utilization of processors.
In running an application on an actual system, the number of CPUs necessary for the system is estimated, and time performance is estimated with a system. For example, Japanese Unexamined Patent Application Publication No. 2012-128771 discloses a method for predicting performance in a multi-tenant environment in which service programs for a plurality of users run simultaneously in a single system. Japanese Unexamined Patent Application Publication No. 2004-213624 discloses a technique for calculating a queue time to adjust the number of threads in a thread pool. Japanese Unexamined Patent Application Publication No. 2000-298593 discloses a queueing model in which a processor conflict due to a plurality of tasks is taken into account to correctly predict the degree of improvement in performance relative to the degree of parallelism and the performance index of parallel computers in a multitask environment.
Queueing theory is often used to evaluate the time performance of systems. However, the queueing theory of the related art cannot predict correct behavior of computer systems having the SMT function described above.